Static random access memories are typically used in preference to dynamic random access memories for one or more of the following reasons: devices having very fast access times (15 nano-seconds or less) are readily available, they require no refresh circuitry or overhead, and ultra-low-power devices are available. There are two types of static random access memory cells in general use today-a six-transistor (6-T) cell and a four-transistor (4-T) cell.
The 6-T SRAM cell, illustrated in FIG. 1, consists of a latch made up of two cross-coupled CMOS inverters. First access transistor Q1, the gate of which is controlled by wordline WL, provides selective coupling of the true digit line D to storage node A, while second access transistor Q2, the gate of which is also controlled by wordline WL, provides selective coupling of the complement digit line D* to storage node B. Optional resistors R1 and R2 introduce response delays in the latch so that if one of the storage nodes A or B is affected by an alpha particle induced single event upset, the affected storage node has a chance to recover before inducing a change in the inverter input values in the other half of the latch, which would cause the latched data to loose its integrity. Since very little power is required to maintain a latched state, 6-T SRAMs are often used for memory in battery applications. They are also the most expensive of SRAMs, as a 6-T cell consumes the largest amount of chip real estate.
The 4-T SRAM cell, illustrated in FIG. 2, is similar to the 6-T SRAM cell of FIG. 1, with the exception that each of the two P-channel transistors of the cross-coupled latch is replaced by a resistive element R3 and R4. Similar to the arrangement shown for the 6-T cell of FIG. 1, optional resistors (not shown) may be placed between the gate of each N-channel transistor and the input node of the other half of the latch to mitigate the effect of alpha particle induced single event upsets. A 4-T cell memory is typically less expensive to produce than a 6-T cell memory because the resistors can be fabricated from thin film transistors in an upper layer. Thus, more transistors (and cells) can be packed onto a substrate. 4-T cell SRAMs are typically not utilized for ultra-low-power applications, as one of the resistors which replaces the P-channel transistors of the 6-T cell is always leaking current to ground. A typical cell array standby current specification for a 4-megabit SRAM device having 4-T cells is generally within a range of 400-2,000 .mu.-amps; for a 4-megabit SRAM array having 6-T cells, the specification is in a range of 10-50 .mu.-amp.
Because of the relatively large number of transistors required to fabricate an SRAM cell, SRAMs are unable to compete with dynamic random access memories (DRAMs) when cost per bit is important, despite the fact that DRAMs require refresh circuitry. What is needed is a static random access memory that is not only more compact than even a 4-T SRAM, but less costly to manufacture.